The present invention relates to a semiconductor device and a failure detection method and relates to, for example, a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure.
It has been required that an AD converter have a low power consumption, a high speed, and a high accuracy. One problem that interrupts the providing of the AD converter with low power consumption, high speed, and high accuracy is a variation among elements such as a capacitor, a transistor and the like that constitute the AD converter.
In general, the accuracy of the AD converter is increased by a method of increasing the sizes of elements and relatively decreasing variation among the elements (hereinafter it may be referred to as an element variation). In this method, however, the size of the circuit becomes large. It is therefore difficult to achieve an AD converter having high speed and low power consumption.
In order to solve the above problem, in recent years, a technique for correcting the element variation in a digital manner has been employed. By correcting the element variation in the digital manner, the sizes of the elements need not be increased. It is therefore possible to suppress an increase in the size of the circuit, whereby it is possible to achieve an AD converter having high speed and low power consumption.
The above method requires, however, a nonvolatile memory or a storage area of a fuse to store a correction value (digital value) of the element variation at the time of manufacturing the AD converter, which increases the cost.
In order to solve the above problem, an AD converter having a digital assist function that calculates a non-linear error caused by the element variation during operation and corrects the non-linear error has been developed. A technique regarding the AD converter including the digital assist function is disclosed, for example, in “Vanessa H. C. Chen and Lawrence Pileggi, “An 8.5 mW 5 GS/s 6b Flash ADC with Dynamic Offset Calibration in 32 nm CMOS SOI”, 2013 Symposium on VLSI Circuits Digest of Technical Papers, pp. 264-265” and “Bob Verbruggen et al, “A 2.1 mW 11b 410 MS/s Dynamic Pipelined SAR ADC with Background Calibration in 28 nm Digital CMOS”, 2013 Symposium on VLSI Circuits Digest of Technical Papers, pp. 268-269”.